CY2XP22 Datasheet | Cypress

Features - - - - - - - - - Pb-free 8-Pin TSSOP package Supply voltage: 3.3 V or 2.5 V mercial and Industrial temperature ranges One LVPECL output pair Selectable frequency multiplication: x2.5 or x5 External crystal frequency: 25.0 MHz Output frequency: 62.5 MHz or 125 MHz Low RMS phase jitter at 125 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.4 ps (typical) Phase noise at 125 MHz (typical): Offset 1 k Hz 10 k Hz 100 k Hz 1 MHz Noise Power - 117 d Bc/Hz - 126 d Bc/Hz - 131 d Bc/Hz - 131 d Bc/Hz Functional Description The CY2XP22 is a PLL (Phase Locked Loop) based high performance clock generator that uses an external reference crystal. It is specifically targeted at Fibre Channel and Gigabit Ethernet applications. It produces a selectable output frequency that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal, the user can select either a 62.5 MHz or 125 MHz output. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP22 has a crystal oscillator interface input and one LVPECL output pair. Logic Block Diagram XIN External Crystal XOUT CRYSTAL OSCILLATOR LOW -NOISE PLL OUTPUT DIVIDER CLK CLK# F _SEL Pinouts Figure 1. Pin Diagram - 8-Pin TSSOP VDD VSS XOUT XIN Table 1. Pin Definitions - 8-Pin TSSOP Pin Number 1, 8 2 3, 4 5 6,7 Pin Name VDD VSS XOUT, XIN F_SEL CLK#, CLK Power Power I/O Type 1 2 3 4 8 7 6 5 VDD CLK CLK# F_SEL Description 3.3 V or 2.5 V power supply Ground Parallel resonant crystal interface Frequency Select: see Frequency Table Differential clock output XTAL output and input CMOS input LVPECL output ..net Cypress Semiconductor Corporation Document #: 001-10229 Rev. - F - 198 Champion Court - San Jose, CA 95134-1709 - 408-943-2600 Revised April 11, 2011 [+] Feedback Frequency Table Inputs Crystal Frequency (MHz) 25 F_SEL 0 1 PLL Multiplier Value 5 2.5 Output Frequency (MHz) 125 62.5 Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM UL- 94 ΘJA[2] Supply...